EDA News Monday October 13, 2003 From: EDACafe _____ Cadence _____ About This Issue SystemVerilog in the news (again) Announcements and pronouncements abound _____ October 6 - 10, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Before you pore through all of this, let me warn you. This is a story without an ending. This week's Press Releases not withstanding (see below), the story of the research and corporate investments in system-level languages, and their subsequent implications in the EDA world, has just barely begun. On the tarmac in Texas Dennis Brophy, the ever politic and positive Chairman of the Accellera language standards body was sitting in an airplane on the tarmac Thursday in Austin, TX, waiting to take off when he was kind enough to put a call through to me via his cell phone. You've just gotta love technology. Dennis was en route home from the first of four SystemVerilog Now! Seminars that are happening this month and next in various venues across North America. He told me that over 70 people had attended the Austin session and that upwards of a thousand people are currently registered to attend the conference across its four locations. I wanted to speak to Dennis about this week's SystemVerilog announcements out of Synopsys and Cadence. The announcements are as follows, abridged as always: The news from Synopsys "Synopsys, Inc. has announced its SystemVerilog Catalyst Program. The Program is open to EDA vendors, silicon and verification IP companies, and training services providers to benefit mutual customers by advancing tool interoperability and the availability of IP using the Accellera SystemVerilog standard. The company says that 30+ companies are announcing their support for SystemVerilog at the program's launch. Corporate members of the Program can gain early access to Synopsys' SystemVerilog-based tools for development and support of their respective SystemVerilog tools, IP and training products." "Current members include 0-In Design Automation, Alatek, Aldec, Aptix, Atrenta, Avery Design Systems, Axis Systems, Beach Solutions, BlueSpec, ChipVision, ControlNet, Doulos, Emulation and Verification Engineering (EVE), GDA Technologies, Interra Systems, InTime, Jasper Design Automation, Novas Software, nSys, Provis, Real Intent, Sequence Design, SiConcepts, Silicon Interfaces, Spike Technologies, Summit Design, Sunburst Design, Sutherland HDL, SynaptiCAD, Tenison, Tera Systems, Tharas Systems, TNI-Valiosys, TransEDA, VeriEZ, Verific, Verifica, Veritable, Veritools, Willamette HDL, and WSFDB Consulting." "Aart de Geus, Chairman and CEO at Synopsys, is quoted in the Press Release: 'SystemVerilog's enhanced design and verification capabilities are well positioned to deliver significant productivity and design quality benefits to the electronic design industry. Synopsys has a strong history of supporting open standards and is launching the SystemVerilog Catalyst Program to help ensure that our customers enjoy the benefits of SystemVerilog, including increased tool and IP interoperability. We look forward to working with current and future members of the SystemVerilog Catalyst Program on this joint effort." The news from Cadence "As part of its strategy to ensure unified standards for advanced design and verification, Cadence Design Systems, Inc. announced support for SystemVerilog. Cadence is committed to accelerating the process of bringing SystemVerilog from a specification to a fully implemented international standard. The initial developer of the Verilog language and a pioneer in the concept of open language standards, as exemplified by the creation of OVI in the early 1990s, Cadence provides current and continuing support for the VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS, and VHDL-AMS standards." "During the next weeks, Cadence will roll out plans for SystemVerilog support in its Incisive verification and Encounter digital IC design platforms, as well as plans for smoothing the path of SystemVerilog through the Accellera and IEEE standards process. To drive this process, Cadence has named Victor Berman, an industry veteran in language standardization, to lead Cadence's language and standardization strategy." "Berman is quoted in the Press Release: 'Cadence supplies a very broad set of design tools and capabilities; my job is to ensure that the semantics of standards implemented at different levels and by different tools can be used together in a productive way. This is best achieved when standards are developed in a unified way with open input from all interested parties. I am looking to the IEEE to provide that unification in the evolution of Verilog.'" "Berman has more than 20 years of experience championing standards issues in the EDA industry, which included the standardization of VHDL and serving as chairman on the IEEE Design Automation Standards Committee for 6 years. To date, Cadence has donated and opened up more than a dozen major proprietary languages and formats to the industry, including Verilog, GDSII and SDF. The Incisive verification platform-the only platform in the industry that supports all broad languages on a single kernel-is working proof of Cadence's commitment to standards." Comments from Accellera First I asked Dennis why he thought Cadence wasn't named as part of the Synopsys program, and why Cadence might suddenly feel the need to issue a Press Release announcing support for SystemVerilog at this particular moment in time. Dennis graciously declined to comment: "It's not really appropriate for me, or for Accellera, to comment on the Cadence announcement. I would prefer you talk to Cadence about that. I don't know what their specific motivations are, but I do know that this stuff is becoming more real [every day]. End users are helping everybody to see what they would like to exploit in the language. We certainly welcome Victor Berman back to the industry. His history in the development of standards is long-standing and well known, and he's trusted by all of us. He'll now be one of the Board Members for Accellera. We've always enjoyed working with him and we look forward to having him on the Board." I asked Dennis why it's important for companies like Cadence and Synopsys to drive and/or endorse the move to SystemVerilog. Is it to protect their ASIC designer customer base or does it reflect a legitimate evolution in the technology? Dennis said, "I definitely think it's part of a legitimate evolution. Designers want their design data and their verification data to be interoperable. People have asked all of us to adopt the whole standard, so that there's a guarantee that any verification data has portability and reuse. It's a pretty pro-designers statement that's being made right now [by way of these company endorsements]. It also represents a broadening of support [for the language]." As I have many times in the past, I asked Dennis to clarify his understanding of the situation twixt SystemVerilog and SystemC. Is there really a battle here or are the two initiatives complementary? Dennis said, "I think the way most of us look at it is that it's complementary, not mutually exclusive. SystemVerilog, in moving from 3.0 to 3.1, now includes direct programming language interfaces, which frankly are C++. If anybody does work with SystemC, it should be easy to reuse that SystemC [design] in the context of a SystemVerilog design. If you're going to do architectural exploration in SystemC, SystemVerilog is a natural companion to SystemC." I asked Dennis to be patient with an additional oft-repeated question: Will hardware and software guys ever communicate? Dennis chuckled: "Well, they all must be doing some of that already because they've sure got lots of electrical devices [out on the market today] with loads of RTOS and software content. I think that system [design techniques] are becoming effective. Could the communication be better? Sure! Can we help to encourage the communication? Yes, we can and I believe we are." Dennis reported on the pulse of things at SystemVerilog Now!: "The mood was very upbeat at the conference. Designers now understand that [SystemVerilog] is an extremely complex language, very content rich. The conference also included a vendor fair, which definitely signals an inflection point from paper specifications into actual product implementation. We've got over 1000 registrants spread across the 4 events this month and I'm predicting that, for the one in Santa Clara on October 22nd, if even just 50 percent of the people who are registered actually show up, that vendors who are there will get more customer contact - more quality customer contact - then many of us have [experienced up until now] by attending DAC." If Dennis is right, maybe you should plan on attending. (Editor's Note: Don't forget that Dennis Brophy also has a day job. He's Director of Strategic Business Development for Mentor Graphics) Comments from Synopsys Meanwhile by way of a phone call later in the day, Farhad Hyatt, Vice President of Marketing for Verification Technology at Synopsys, answered some of the same questions that I had asked Dennis Brophy earlier: "The SystemVerilog standard was ratified by Accellera in May. Our tools are just now becoming available [that support the language]. By establishing the SystemVerilog Catalyst Program we wanted to make sure that the other EDA tool vendors can provide the tools that will work with our tools in synthesis and verification. Obviously, there's a huge momentum behind the move to SystemVerilog. Close to 40 vendors have come out pledging support for the language. The fact that so many vendors are looking to support the standard is a testament to what's going on with their customers." "Our intent is to create interoperability with Synopsys tools. Synopsys has many open programs for interoperability - for instance the inSync program, which is designed to ensure interoperability between Synopsys tools and third-party tools. Our efforts with the Catalyst Program are absolutely not redundant with Accellera's efforts - this is a completely complementary effort to Accellera's efforts. Accellera's charter is to work towards evolving EDA standards. Synopsys' charter is to build tools that adhere to that standard. Ours is an open program. So when companies like Mentor Graphics and Cadence are ready to participate, we will be happy to talk with them as well." Comments from Cadence Paul Estrada, Corporate Vice President of Strategy and Market Development at Cadence, was also willing to answer some questions by phone - particularly the 'Why now?' with regards to this week's SystemVerilog announcement from Cadence: "We've had lots of conversation with customers over the last few months while this standards stuff has been going on, and we've been listening to them. There are some customers who think there should be one Verilog and there are some customers who don't. Some really like the idea, others don't. Some just don't care." "At Cadence, we believe that supporting SystemVerilog doesn't mean we're not supporting customers who don't like it or aren't interested. Right now, many hope that SystemVerilog will subsume the Verilog functionality, knowing that there are still many questions that need to be ironed out in that process. We've been pushing from the beginning to have Accellera work closely with the IEEE standards [committees], and although the timeframe is still somewhat open, [we're pleased to see that interaction happening]. [In part that is what has prompted our SystemVerilog announcement.]" "Meanwhile, we see in the Synopsys [position] an [assumption that] the whole world will move to SystemVerilog. But here at Cadence we don't believe [that will happen]. There's a whole other world out there that's simply not interested. Currently, we have no immediate plans to join the Synopysy SystemVerilog Catalyst Program. In any case, they might have competitive issues even if we wanted to as they're providing interoperability through the program to their own tools." "But there still remains a whole world out there that doesn't use Verilog. They're using SystemC or other languages. SystemC is an extension of the C++ language and libraries. Many people who are doing system verification for design are using C-based languages and know nothing about Verilog or VHDL. They're working with big test structures and see their methods as a natural way to build a test environment." "Design is a complex world. Our long-term position is to support the standards - VHDL, Verilog, VHDL-AMS, Verilog-AMS, PSL, SystemC, and now SystemVerilog. Basically our position remains clear. There are a number of standards out there that the entire design community is interested in. We'll support all standards, including SystemVerilog, that are economically feasible. But we'll always continue to give people a choice depending on what their needs are." Comments from Tenison EDA David Greaves is a Professor in the Computer Science Laboratory at Cambridge University in the U.K. He is a well-spoken academic, someone who chooses his words carefully. He's also the founder of several successful companies, including Virata (founded in 1993, a $500 million IPO in 2000) and Tenison EDA (founded in 2000). David spoke to me by phone from his office in William Gates Hall, home of the Computer Science Department at Cambridge. I asked him to address some of the same questions I had put to Accellera's Dennis Brophy, Synopsys' Farhad Hyatt, and Cadence's Paul Estrada. Here are David's comments, laced with commentary and a bit of historical perspective: "Historically, Prolog has been the only widely known logic programming language, but we are seeking today to bring logic programming to system synthesis. I first heard of Verilog when I was at Silicon Graphics back in 1988. Silicon Graphics was among the earliest adopters of Verilog. I wrote a Verilog compiler for FPGA targets while the industry was still promoting gate-level schematic entry for FPGAs. I started teaching Verilog at Cambridge in 1993. At Virata, we used it both for FPGA and ASIC design. In 1998, I wrote a simple program that generated C code from Verilog, which we used at Virata to translate some parts of our designs into C. That led to the founding of Tenison." "In terms of being a general purpose programming language, Verilog has many deficiencies, including a general lack of features, or the potential to simulate differently from synthesis. The current hardware design methodologies using Verilog are simply ridiculous. We ask our engineers to encode a design at a low level and in a massively parallel way. RTL design techniques force a designer to think of a whole system as a hardware system. But [in actuality], it's much easier to write software than to write hardware." "SystemVerilog is a good step towards closing the difference between general purpose languages and HDLs - its assertion capabilities add another dimension to the language. SystemVerilog may be an evolutionarily legitimate step, provided it is eventually defined as a semantically clean language. Otherwise, it will just be another language - good for hardware design, but one with unpredictable properties and missing features. I have spoken about synthesis from assertions, but this is probably a long way off from reality, despite being an interesting and desirable end point." "Both SystemC and SystemVerilog are block-structured imperative languages that can be traced back to Algol 68. There's certainly not a lot in either of those languages that's either new or trendy, although they are both worthwhile steps forward. SystemC is really just C++, so it can be more easily integrated with software design and front-end architectural exploration. SystemVerilog is be more easily integrated with back-end low-level hardware aspects of design such as timing closure. Both SystemVerilog and SystemC provide a means of bridging the gap between what hardware engineers do and what the software people do. Although, in actual fact, the industry is being very slow to pick up on that." "From Tenison's point of view, using our products you can take your handcrafted hardware design and convert it into SystemC and then your software people can interact with the SystemC. The automatically generated SystemC is not actually being used to design anything. But it can be substituted into the testbed in SystemC and used for architectural exploration. There's no reason why the compilation of SystemC to hardware can't be used, but I think the current generation of workstations is not generally up to producing acceptable designs." "I think that most hardware and software design will be increasingly done using fully integrated tool chains. These tool chains will aim to fully support co-design through automatic partitioning between the hardware and software. However, those facilities will go largely unused initially in that designers will continue to have, at the time of design entry, a very clear idea about what is going where. As compiler power increases with increasingly [sophisticated] workstations, however, high-level design and automatic synthesis will become increasingly successful. We can see that endpoint out there today, so I [strongly] recommend designing tool chains that head for [that endpoint]." "ASIC designers will continue to see their role changing over time. Today, there can be a pretty big separation between the layout, testability/test, and design teams. Perhaps [going forward], the design engineering team will need less and less contact with the back-end people as VLSI design becomes more and more turnkey." "Currently at Cambridge, we teach Verilog and ARM Assembler to all of our second year Computer Science undergraduates. They get to build hardware and software to interact with each other at the bus interface level. In the course of their 3-year undergraduate program at Cambridge, students are required to learn ML, Java, and Verilog. They are not required to learn C, but the commercial pressures of employment require that everyone learn C nonetheless. We also have a course on comparative languages where we detail the differences - for instance, the ability to have dynamic free variables or to cleanly support remote procedure calls and so on." "Here at Cambridge, we have one of the most famous Computer Scientists in the world, Robin Milner, who basically invented process algebra together with Tony Hoare, who is now across the street at the Microsoft Lab. Many of the world's experts in programming language design have moved here and are now in one of our two research groups. Cambridge [is emerging] as the world's hotbed for advanced studies of new language concepts." "Currently, all of my new graduate students are working on high-level specification languages, the language constructs that are necessary for system specification. Creating a new language means different things to different people. [In a university setting], new languages are sketched out on white boards every day. However, it's a very different thing to translate those sketches into an industrial-strength standardized language." Industry News -- Tools and IP Agilent Technologies Inc. announced that Thine Electronics Inc. has selected Agilent's high-frequency EDA tools to "help speed RF integrated circuit (RFIC) design." Kazutaka Nogami, Director of Business Unit III at Thine Electronics, is quoted in the Press Release: "The ability to perform high-speed, frequency-domain simulation with Agilent's EDA tools has played an important role in the early release of our handset buffer amplifier RFIC, which was announced in July." Applied Wave Research, Inc. (AWR) and Sonnet Software, Inc. announced a circuit-to-EM integration. The companies say the integration will allow monolithic microwave integrated circuit (MMIC), radio-frequency (RF), and microwave engineers to translate circuit layouts between AWR's Microwave Office design suite and Sonnet's em software with the AWR EM Socket interface. Per the Press Release, "The EM Socket interface enables the Microwave Office software to directly interface with Sonnet for EM simulation. Users design in the Microwave Office environment and invoke Sonnet's EM solvers from a single user interface. Users familiar with Sonnet's XGEOM editor can also use this editor. Circuit layouts and simulation results are embedded directly into the Microwave Office object-oriented database." ASSET InterTech announced new features in their ScanWorks boundary-scan test and programming environment. The new productivity technology, which is called TopCAT (Topology and Cluster Analysis Technology), is included in the latest version of ScanWorks, Version 3.3.2. TopCAT analyzes the schematic of a PCB to identify all of the non-boundary scan devices that are connected to boundary scan devices. These non-boundary scan devices are candidates for boundary scan cluster tests. Next, TopCAT automatically matches the names of the non-boundary scan devices in the design's netlist with device models archived on ASSET's web site or stored in a model library within the user organization. Once the device models have been retrieved by ScanWorks' TopCAT technology, they are automatically included in the interconnect test generation process. Lastly, TopCAT optimizes the configuration of the device models in a test action for the highest test coverage and to ensure the safety of the board. Atrenta Inc. and Aptix have announced a partnership to develop a set of RTL coding rules for pre-silicon prototyping that the companies say will ensure efficient mapping to Aptix's multi-FPGA prototyping platform. The rule-set is made available as the Aptix Policy for Atrenta's SpyGlass Predictive Analyzer, and is targeted for both design and verification engineers. The tool is intended to help both groups follow best practices and ensure code compliance with design-for-prototyping principles. For designers it provides a comprehensive set of rules around which to efficiently code their RTL for FPGAs. For verification engineers it ensures that they are receiving clean RTL while providing in-depth design information. Charlie Miller, Senior Vice President of Marketing & Business Development at Aptix, is quoted in the Press Release: "Aptix has more experience in pre-silicon prototyping than any other company. Part of our expertise is knowing the best way to design for prototyping. This new Aptix Policy for Atrenta's SpyGlass Predictive Analyzer captures that knowledge for use by our mutual customers." Barcelona Design Inc. announced that Sandbridge Technologies has licensed its analog synthesis solution for the fast creation of PLL circuits. Gary Nacer, Director of Engineering at Sandbridge, is quoted in the Press Release: "Because we serve the wireless handset market, power is of ultimate concern. Barcelona Design's synthesis solutions can generate full-custom PLLs, which satisfy our tight power budget while still meeting required high-performance specifications." Also per the Press Release, the PLLs will be generated using Barcelona's PLL synthesizer for the TSMC 0.13-micron "G" process. Sandbridge will use the circuits in its new SandBlaster DSP products for the wireless terminal market. Giga Scale Integration Corp. (Giga Scale IC) introduced Time Architect, which the company describes as a "new class of electronic system level (ESL) virtual prototype software for fast, accurate estimation of chip size, power, cost and yield. Time Architect provides the umbrella over ESL design common in today's high-end ICs, and opens a new software category for the EDA industry. It allows electronic specification development for complex SoCs with full knowledge of the IC supply chain of libraries, memories, and IP. Specification can be evaluated for cost, size and power requirements. Finally, it obsoletes traditional IC-estimation methods that have evolved from pencil and paper to spreadsheet. Time Architect is based on Giga Scale IC's Technology Macro Modeling (TMM) for three to nine layers of metal, and process feature sizes ranging from 90 nanometers to 0.25 microns. TMM interprets standard data - LEF or Liberty, for example - describing semiconductor processes, libraries and IP to produce accurate macro models for area, power, clock and density evaluations." Magma Design Automation Inc. and Semiconductor Manufacturing International Corp. (SMIC), described as the largest foundry and ASIC design services provider in China, released a validated reference flow that incorporates the Magma IC implementation "solution." The entities say that the flow was developed and validated using SMIC's 0.18-micron process technology using two SoC designs, and that support for other SMIC process technologies will be developed based on customer demand. Lung Chu, Vice President of Asia-Pacific Operations for Magma, is quoted in the Press Release: "We're pleased to partner with SMIC on this reference flow. I believe it will help our mutual customers achieve their area, timing, power, performance, manufacturability and reliability goals. This partnership, along with the technical support we are able to provide through our offices in Beijing, Shanghai, and Shenzhen, allows Magma to better support its customers in China." Also from Magma - in a joint announcement with UMC, the company announced the availability of "the first fully validated, proven-in-silicon RTL-to-GDSII reference flow slated for chip designers utilizing UMC's 0.18-micron, 0.13-micron and 90-nanometer process technologies." The flow can be downloaded from either company's website. The companies report that two mutual customers that have implemented designs using the RTL-to-GDSII flow include WIS Technologies and Faraday. MIPS Technologies, Inc. announced that Fodus licensed the MIPS32 4Kc-processor core to develop SoCs for wireless routers, incorporating 802.11b/a/g wireless LAN access points, Ethernet switching routers, and firewall and VPN functions into one chip. Jeff Jen, President and CEO of Fodus, is quoted in the Press Release: "MIPS Technologies' highly scalable architecture gives our company the flexibility to upgrade future designs with minimal development effort." Synopsys, Inc. announced the availability of key components of Synopsys' Galaxy Design and Discovery Verification Platforms on Intel Itanium 2-based systems running the 64-bit Linux operating system. Rich Burnley, Director of CAD at Xilinx, is quoted in the Press Release: "In order to achieve the capacity we require to verify our latest programmable logic devices, we are running VCS 7.1 on 64-bit Linux systems based on the Itanium 2 processor." Synplicity Inc. announced it has made several "quality of results (QoR) improvements" to its Synplify and Synplify Pro FPGA synthesis software to provide "increased performance and area reduction for Xilinx devices." The company says the latest versions of Synplify will "enable designers to increase the timing performance for their Virtex-II Pro devices by an average of nearly 10 percent compared with the previous version of the Synplify software. Additional enhancements to the software have been implemented especially for use in conjunction with Xilinx's recently announced Integrated Software Environment 6.1i (ISE). With these optimizations, designers can obtain significant area reduction in their devices often enabling them to use a smaller, less costly device, potentially saving tens or hundreds of thousands of dollars in device costs." True Circuits, Inc. (TCI) announced the immediate availability of a line of Delay-Locked Loop (DLL) analog hard macros for high-speed, DDR-style (double data rate) interface applications. Per the Press Release: "True Circuits' DDR DLL uses a reference clock to establish a time base in order to delay arbitrary strobe signals by precise fractions of the clock cycle. It uses an analog delay line that is phase-locked to be insensitive to temperature or supply voltage and setup with very high supply noise rejection. The block can be configured by TCI to have just about any number of slaves (which delay the arbitrary signals) with a single master section to minimize area and power. The slave delays can be set to particular values or dynamically adjusted after determining the boundaries of a data eye." The X Initiative, a semiconductor supply-chain consortium, announced that X Initiative co-sponsor Toshiba Corp. has produced the industry's first functional silicon for the X Architecture. The entities say that the fabricated 90-nanometer functional test chip confirms the wire-length and via reduction benefits of the X Architecture and completes the X Initiative's roadmap for preparing the semiconductor design chain for production fabrication of X Architecture chips. The X Initiative also announced that Toshiba has been given the 'X Architecture Pioneer' award. The X Architecture represents a new way of orienting a chip's microscopic interconnecting wires using diagonal pathways, as well as the traditional right-angle, or "Manhattan," configuration. By enabling designs with significantly less wire and fewer vias (the connectors between wiring layers), the consortium says the X Architecture can provide "significant, simultaneous improvement in chip performance, power consumption and cost." The five-metal-layer Toshiba test chip was fabricated in Toshiba's 90-nanometer semiconductor process, using its standard process, equipment and materials for this node. The Press Release says, "Compared to a Manhattan version of the same design, the X Architecture implementation required 14 percent less total wire length and 27 percent fewer vias. For the past 20 years, chip design has been primarily based on the de facto industry standard 'Manhattan' architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three." Also from Toshiba - TAEC (Toshiba America Electronic Components, Inc.) announced details of its SoCMosaic custom chip hardware/software (HW/SW) co-development strategy, which the company says is "designed to help software engineers developing code for an SoCMosaic custom chip significantly reduce software development time by as much as one year." Toshiba also announced the selection of WhiteEagle Systems Technology SwordFish Emulation Platform and the Mentor Graphics Corp.'s Seamless Version 5 co-verification tool as its first two co-development environments. The company says that, compared to conventional approaches, the SoCMosaic custom chip HW/SW co-development environment allows software development to begin as much as one year sooner. Customers can run their software on the SoC while it's in development, executing code on a functional model, a mixed function/register-transfer level (RTL) model and an FPGA emulator that achieves 10 percent of the clock speed of the final SoC. Software engineers can use the same programming and debugging environment throughout the entire process, from the C model all the way to the working end product. UMC announced that it has expanded its availability of ARM core offerings with the licensing of the ARM926EJ core. The companies report that "this IP core brings the total number of ARM core-based processors that UMC is able to make available to its customers to five. UMC already offers the ARM7TDMI core, the ARM922T core, the ARM946E core, and the ARM1022E core through its Gold IP program. Verisity Ltd. announced a "first-of-its kind verification management solution." Per the Press Release, the company's vManager enables "predictable verification closure of highly distributed, multi-level verification activities and optimal resource utilization. vManager enables project teams to deploy metric-driven processes that start from an executable specification of functional requirements and coverage plans, and then optimally directs verification resources towards total coverage and closure. To facilitate optimal deployment of verification environments and compute resources, vManager filters and analyzes the enormous amounts of verification data created every hour, of every day. It then annotates and correlates the results against verification runs, and displays various views of the project's progress towards verification closure." VeriSilicon, Inc. and Legend Design Technology, Inc. announced support for instance-based characterization of Verisilicon embedded memory. You-Pang Wei, President and Chief Executive Officer of Legend Design Technology, Inc., is quoted in the Press Release: "Due to second order effects such as coupling and leakage power inherent to deep sub-micron designs, instance modeling of embedded memories is required for an accurate pre-tapeout system simulation. Users of Verisilicon memory compilers now have a reliable and cost-effective turnkey solution for maximizing their design's performance and yield in silicon." Virage Logic Corp. announced that it has expanded its licensing agreement with NEC Electronics to include Virage Logic's Non-Volatile Electrically Alterable (NOVeA) embedded memories. NOVeA is described as "the first embedded non-volatile memory (NVM) that is manufactured on a standard CMOS logic process without any additional masks or process steps." NEC Electronics has qualified Virage Logic non-volatile memories for its 0.15-micron CMOS logic process. Newsmakers Yet another acquisition has been announced this week (although, this one might be viewed more as a merger). TNI-Valiosys has acquired TransEDA. The companies say they will merge their operations "to provide solutions for the growing validation challenge and to provide joint customers with a ready-to-use, structured verification environment." Under the terms of the agreement, TNI-Valiosys has acquired all shares of TransEDA Technology Ltd. from TransEDA PLC. Meanwhile, both companies will continue to operate, providing "uninterrupted development and support of their complete product lines to their existing customer base." Following the merger, TNI-Valiosys' and TransEDA's personnel (40 persons and 35 persons, respectively) will be integrated into one single team and continue to operate from both companies' existing R&D sites. Starting in Q1 2004 all TransEDA and TNI-Valiosys EDA products will be sold under the TransEDA name and supported by the TransEDA and TNI-Valiosys global network. TNI-Valiosys' President and CEO, Marc Frouin, becomes President and CEO of the new TransEDA. Both companies' management teams will be combined under the direction of Modesto Casas for Sales and Marketing and Frederic Rocheteau for Product Development. TransEDA's CTO John Colley will continue to lead the strategic development for the new company. TNI-Valiosys is located in Paris, France. TransEDA is located in Eastleigh, U.K. Accellera and the IEEE Standards Association (IEEE-SA) announced that Accellera's Advanced Library Format (ALF) has been approved as IEEE 1603-2003. IEEE 1603 standardizes the language and semantic representation for design libraries. It supports an RTL-to-GDSII description of functional, electrical performance, and layout views for technology libraries, scalable from cells to complex hierarchical design blocks. In addition, the VHDL and Verilog RTL synthesis standards have passed balloting and are now IEEE 1076.6-1999 and IEEE 1364.1-2002, respectively. These standards define the syntax and semantics that can be used by all compliant RTL synthesis tools to achieve uniformity and interoperability. Meanwhile, the IEEE 1076-2002 standard includes three enhancements - The definition of concatenation and real types improves portability among tools. VHDL now supports multi-byte characters within comments, which allows users to document their designs in their native language, such as Japanese, Korean and Chinese. And buffer mode ports are improved so that they can be easily used with OUT or INOUT mode ports. When designing library components or designing a block that uses library components, this change makes it easy to use a single coding style (single port type) that can be used in any context. E*ECAD, Inc. announced that it has signed a software and distribution partnering agreement with Translogic. Translogic now offers monthly and perpetual licenses of its graphical design entry product EASE through E*ECAD's online sales and distribution channel. Magma Design Automation Inc. announced that the company's headquarters have moved from Cupertino to a larger facility in Santa Clara, which can accommodate 400+ employees, new R&D labs, and a larger training center than in the previous facility. Milan Lazich, Vice President of Corporate Marketing for Magma, is quoted in the e-mail that accompanied the Press Release: "Magma is moving its corporate headquarters next week from Cupertino to Santa Clara, a mere 10 miles away, but miles from where it's come since it was founded in 1997. Magma's new corporate headquarters, which will house 300 employees initially, is a four-story, 130,000-square foot building formerly occupied by 3Com. The two-story building in Cupertino saw Magma through its early years, growth spurts and its IPO two days before Thanksgiving 2001. Since then, Magma has continued to advance, despite the economic climate, achieving record revenue in its most recent quarter. The decision to relocate its headquarters was made for a variety of business and practical reasons, and puts Magma closer to its Silicon Valley customers. Perhaps most interesting - or symbolic - is Magma's new positioning. It will now sit squarely between its two largest competitors, Cadence and Synopsys. The rivalry between the three is fierce and only getting fiercer. Magma, with its new highway frontage on Route 237, will now be perceived as moving up in the EDA industry and one of the leaders." Mentor Graphics Corp. announced it has acquired FirstEarth, a U.K.-based software company specializing in the supply of analysis software for design of electrical wiring systems used in automotive, rail and aerospace markets. FirstEarth products are already integrated with Mentor's Logical Cable schematic authoring tool and will be available through Mentor's direct channel immediately. Terms of the deal were not disclosed. FirstEarth was established in 1997 to develop and market software to automate Failure Mode and Effects Analysis (FMEA) and Sneak Circuit Analysis (SCA) for electrical systems. ReShape, Inc. announced that Mark Bales has joined the company. Previously Bales was an R&D Fellow at Cadence Design Systems. In 1983, Bales co-founded SDA Systems, one of the precursor companies to Cadence, and in 1992 was a co-founder of HLD Systems. Most recently, Bales was heavily involved in the OpenAccess Design Database and a chief architect of the OpenAccess Change Team, the industry group that controls the evolution of the OpenAccess standard for interoperability among EDA vendors. Prior to Cadence, Bales worked at Hewlett Packard, Tektronix, and IBM. He has worked in EDA since 1979, and has a BSEE and an MSEE from U.C. Berkeley. Joe Mastroianni, Vice President of Engineering at ReShape, told me by phone, " In a small company, the titles are fluid. You could consider Mark Bales as a Fellow of the company, but our CTO could also be seen in that light. [Titles aside], Mark will be a big contributor to ReShape. And the fact that Mark and Board Chairman Dave Gregory were respectively involved at the inception of Cadence and Synopsys means that they're both familiar with the process of bringing products from conception through to market. Of course, we all know that Synopsys and Cadence tend to do things in slightly different ways, so we expect that ReShape will benefit from having both points of view here." "I doubt there will be any difficulty for Mark to transition to working in a small company. He was with SDA at the beginning - was actually in Jim Solomon's living room when the concepts for SDA were being developed - and is quite familiar with the dynamics of a small company. He was also a founding member of HDL with George Janac. I think Mark's got exactly the correct perspective for our situation here. He's got a really good grasp of what it takes to create an 'infrastructure' - although I'm reluctant to use that word - in that he's written three commercial-grade databases. He'll definitely be able to contribute to our infrastructure and database. He brings a great perspective on what the industry needs, especially though his experience with OpenAccess. ReShape is currently based on our ability to bring third-party tools together and leverage them for our customers. Marks knows how to determine what customers need in a CAD environment, how to store their data, and how to present things in a logical way. [In deciding to join ReShape], he took a look at our systems and felt he could help us out in all of these areas." VSIA (Virtual Socket Interface Alliance) and OCP-IP (Open Core Protocol International Partnership) announced a "strategic" alliance intended to jointly support the OCP socket and socket interface as an industry standard. Under this agreement, VSIA now endorses the OCP socket and OCP-IP becomes the first VSI Alliance Adoption Group continuing to focus on tools and support to promote the adoption of OCP. Additionally, OCP-IP receives "stewardship" of the previously developed VSIA Bus Attributes Specification and VCI Bus Interface Standard. As a result of this agreement, VSIA members are now granted free access to the OCP Standard. In anticipation of this agreement, OCP-IP has already merged the essential features of VCI into OCP 2.0. Michael Kaskowitz, VSIA President, is quoted in the Press Release: "OCP-IP has done a tremendous job in gaining industry respect and momentum for the OCP Standard. We endorse this standard and support its adoption through the formally identified Adoption Group. We will be announcing other Adoption Groups that will support industry standards developed by VSIA or other respected groups." Ian Mackintosh, President of OCP-IP, is also quoted: "As the only open, fully supported industry standard socket, it is a natural evolution that the OCP standard is endorsed by VSIA. We look forward to continuing our already extensive work in evolving the OCP Standard and its supporting infrastructure and hope that this example will lead the way for similar industry collaborations." Silvaco International announced that it has acquired the assets of Simucad Inc. Simucad is a provider of Verilog logic and fault simulation software and was founded in 1981. It has a current user base of 9,000+ design engineers. The Press Release says that Simucad employees have relocated to the Silvaco Santa Clara, CA., campus for integration with Silvaco's product development, sales, and customer support teams. Meanwhile - X-FAB and Silvaco announced an agreement to provide mutual customers with analog/mixed-signal process design kits that the companies say will result in "higher design productivity." These kits will support Silvaco circuit simulation and IC CAD tools on X-FAB's XC06 processes. Virage Logic Corp. announced the company has appointed Richard Lanham as Director of Japan Business. Lanham has 30 years' experience in the EDA and semiconductor IP industries in Japan and North America. Previously Lanham was with Cadence, Daisy Systems, and Meta-Software. He is quoted in the Press Release: "I look forward to further developing the partnerships Virage Logic has established with such Japanese market leaders as NEC, Fujitsu, Kawasaki, Oki, Rohm, Sharp, Sony and Toshiba to enable them to deliver even more innovative products. And, our establishment of dedicated customer support in Japan underscores our commitment to our customers in this important market." Also from Virage Logic - The company announced it has broadened and renamed its partner program and has added 16 new members. The Virage Logic IP (VIP) Partner program replaces the Memory Alliance Program (MAP), originally established in March 2001, which the company says will "better support" the needs of Virage Logic's semiconductor IP platform customers. Greer Person, Vice President of Business Development for Virage, is quoted in the Press Release: "System-on-chip design encompasses many decisions and activities beginning with system-level conceptual design and ending with the shipment of packaged, tested parts. Our objective is to ensure that our customers move through this process as efficiently and reliably as possible." In the category of ... Can M&A be a two-way street? Giga Scale IC was announced last week as a spin-out of InTime Software. George Janac, formerly of InTime, but now of Giga Scale, and Bob Smith, now head of InTime made the following comments during a phone call this week, patiently answering yet more questions related to their business move. I asked them if they were going the wrong way on the one-way M&A street. Janac said, "In some sense [the spin-out of Giga Scale from InTime] is linked to the history of the dot.com era. [At the height of the boom], there were lots of companies merged together that didn't belong together, companies that had little in common. But now, particularly in telecomm, you're seeing disaggregation coming back - for example the Motorola announcement this week (see below). InTime had grown fairly large, with our biggest opportunity being in the RTL timing analysis and floorplanning market. But [we wanted] Giga Scale IC to concentrate on a new market, the chip coding, system archtecture, and specification market. We were looking at tools for use early in the design process, what is a part going to cost, what is the best combination of libraries, process, memory for that chip. So I purchased the Giga Scale IC assets from InTime through a Series A buy-out - although I still have a role at InTime. These are interesting times, however, and we feel that what we're doing here [with this spin-out] is what's best for the shareholders of both companies." Smith said, "Focus is the operational word here, as opposed to during the dot.com mania when there wasn't such a big expectation to rapidly turn a profit in a new business. Frankly, for instance, a company like Magma started when there was ease in raising lots of money." "Today, however, the focus is on profit - Cash is King. InTime started with a compelling vision to address lots of things, however there [turned out to be] two markets [in the equation here]. It's too much to ask of our investors to have the one company [playing in two markets]. Although people are still very cautious today about spending, we are starting to see more project activity. Things are starting pick up a bit on the semiconductor market, and the broader markets are not doing too badly. But focus is still [the most important factor] in business decisions. Providing product focus means understanding our customers and their problems. Asset Light at the end of the tunnel Motorola, Inc. announced that the company intends to separate its semiconductor operations into a publicly traded company. The announcement generated quite a bit of interesting in the technical and business press. The Press Release says, "This action reflects Motorola's intention to increase its focus on communications and integrated electronic systems, as well as create an exciting opportunity for the company's Semiconductor Products Sector (SPS) as an independent semiconductor company with its own focused strategy. Motorola has not finalized details of the transaction. Over the last several years, SPS has successfully executed an 'asset light' business model that differentiates it from other semiconductor players." "This business model combines a balance of shared cost in developing advanced technologies, revenue from the licensing of intellectual property and more new product offerings than it has in the past across its leading positions in wireless, networking, transportation and standard products. With its own publicly traded equity, SPS will have the opportunity to pursue acquisitions, should it so choose, of additional strategic product lines and technology using semiconductor equity valuations instead of the blended equity valuation of Motorola. In addition, the semiconductor industry cycle appears to be in an upswing; therefore, Motorola believes the time is right to take these actions. Motorola is considering an IPO of a portion of SPS, followed by a distribution of remaining shares to shareholders in a tax-free manner, subject to Motorola board approval, favorable market conditions, regulatory approvals and other customary conditions." What a difference a week makes It's been a gut wrenching few days for Northern Californians. Who cares, you may ask. The bulk of the world doesn't live in Northern California. Yeah that may be true, but every Captain of (high-tech) Industry will tell you - as they tell me all the time - that they've just gotta have an office here in Northern California, that having a corporate presence in Silicon Valley, the epicenter of all things state-of-the art, is absolutely essential if one hopes to be perceived as a 'real' player in 'the industry.' Okay, so what's been so gut wrenching over the last few days for the poor souls who inhabit this place? Well, first and foremost the Giants fell to the Marlins. That alone brings life as we know it to an end. Second of all, the A's fell to the Red Sox. Now the A's may be the also-rans in the race to win the hearts and minds of the Bay Area, but they're a pretty good surrogate when the Giants can't pull it off. But they lost nonetheless, and bitter grief has turned to inconsolable anguish. Finally, as if all of that baseball pain wasn't enough, Northern Californians chimed in Tuesday on the gubernatorial recall and said "No," but were resoundingly shouted down by the remainder of the state (short of the City of Angels). A new Governor-Elect is revving up at least one his many Humvees and is setting his GPS to help him find Sacramento. Oh my. Who would have ever thought? Now, suddenly, you've got the specter of zillions of highly educated, technically savvy individuals running around Silicon Valley wondering how, oh how, did a guy who probably can't distinguish between silicon and silicone become the governor of what is being described as the 6th largest economy in the world - an economy that contains at least one of every conceivable fruit of the plethora of fruit that constitutes the picturesque cornucopia of the semiconductor industry. Well, who knows? Perhaps there are more surprises in store for Northern California. Perhaps it's not really the beginning of the end. In Thursday's San Francisco Chronicle, Mr. Schwarzenegger is portrayed on the front of the business section in a full-page, full-length photo, clean shaven, hair neatly combed, shirt and tie gloriously coordinated with an expensive, well-cut suit, cuffs carefully breaking on polished leather. Short of the famous head on those broad shoulders, he could easily be anybody's CEO - proud, confident, smooth, well-dressed, ready to present the keynote at the latest Entrepreneurial Business Forum or Venture Capital Confab. And to add to the image, his photo is surrounded by articles with advice for the new governor from leaders in Silicon Valley. They suggest he reduce the costs of doing business in the State. They suggest he work to stem the drain of business out of the State. They suggest he move to increase the quality of education across the State. They suggest he tap into the brain trust in Silicon Valley itself, a brain trust that sits ready and waiting and anxious to help. In fact, they seem to be suggesting that he may be just what the doctor ordered - a potentially galvanizing leader who can brings zest and optimism back to the Capital and to the State. Yet, they didn't vote to elect him. California needs a shot in the arm. A kick to the head. A boot to the butt. A slap in the face. California needs to buckle up, calm down, work hard, come together, think as a team. We need to hope that the Red Sox beat the (odious) Yankees. That Chicago puts Florida in its place. That the Red Sox and the Cubs meet head-to-head and that finally, finally our beloved Dusty Baker gets his World Series ring. We need to hope that all of this can happen, that Happy Days are Here Again. We need to believe that California will rise again. We need to believe that even if it's bottom of the 9th with two outs and the home team down by a run, that the other guys will finally be courageous enough to pitch to Bonds, that the runner on 2nd will score, and that Bonds himself will come across home plate with his distinctive victory fists pointing high to the sky. We need to believe we can win once again. Because everybody wants to look like a winner and image is everything. --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are subscribed as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your subscription details, including format and frequency, or to unsubscribe, please click here or visit http://www10.edacafe.com/nl/newsletter_subscribe.php. If you have questions about EDACafe services, please send email to edaadmin@ibsystems.com . Copyright c 2003, Internet Business Systems, Inc. All rights reserved.